It is desirable for many digital signal processing applications to shape a two-phase clock signal having an incoming non-symmetrical waveform in order to provide a symmetrical or "square wave" output, in which each half of the duty cycle equals the other half. One known way to provide such an output is to apply a phase locked loop to double the incoming clock frequency and then divide the output of the phase locked loop with a divider, such as a D flip-flop. The drawbacks of this approach are that it is complex and therefore expensive in terms of costs of implementation and "real estate" of integrated circuit arrays.
It is also known to form a digital circuit using an exclusive-OR gate having one input connected to an incoming signal stream, and having another input connected through a delay element to the same incoming stream. If the input to such a circuit is a 50% duty cycle clock, the output is a clock at twice the frequency, with a duty cycle ranging between 20% and 80%. If, for example, it is assumed that the delay element provides a delay which is nominally 40% of the period of the outgoing clock, process variations in forming an integrated circuit containing the delay will result in a delay which is as small as one half, or as large as two times, the nominal 40% delay. Because a worst case or 20% duty cycle clock is unacceptable for most applications (and effectively prohibits further multiplication), a hitherto unsolved need has arisen for a simplified and improved method and circuit for altering the duty cycle of the exclusive-OR gate to provide an equalized duty cycle output.